View SIC462ED-T1-GE3_8837992.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 1 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 4.5 v to 60 v input, 6 a synchronous buck regulator description the sic462 is a wide input voltage high efficiency synchronous buck regulator wi th integrated high-side and low-side power mosfets. its power stage is capable of supplying 6 a continuous current at up to 2 mhz switching frequency. this regulator produces an adjustable output voltage down to 0.8 v from 4.5 v to 60 v input rail to accommodate a variety of applications, including computing, consumer electronics, telecom, and industrial. sic462s architecture delivers ultra-fast transient response with minimum output capacitanc e and tight ripp le regulation at very light load. the device is stable with any capacitor and no external esr network is required for loop stability. the device also incorporates a power saving scheme that significantly increases light load efficiency. the regulators integrates a full protection feature set, including over current protection (ocp), output overvoltage protection (ovp), short circuit protection (scp), output undervoltage protection (uvp) and thermal shutdown (otp). it also has uvlo for input rail and a user programmable soft start. the sic462 is available in le ad (pb)-free power enhanced mlp55-27l package. features ? single supply operation from 4.5 v to 60 v input voltage ? adjustable output voltage down to 0.8 v ? 6 a continuous output current ? adjustable switching frequency from 100 khz to 2 mhz ? adjustable current limit and soft start ? 98 % peak efficiency ? ultra-fast transient response ? 1 % output voltage accuracy ? normal, ultrasonic or pulse skipping operation ? 5 a shutdown current ? 250 a operating current ? cycle-by-cycle current limit ? output overvoltage protection ? output undervoltage / short circuit protection ? output voltage tracking and sequencing ? scalable family of output current: ? 3 a (sic463), 6 a (sic462), 10 a (sic461) applications ? pols for telecom ? industrial and automation ? industrial computing ? consumer electronics ? ? ? ? ? ? ? ? typical application circuit and package options fig. 1 - typical application circuit for sic462 v in p g ood en v dd s w p g nd a g nd p g ood enable v out v fb boot ss v s n s f s w i limit pha s e comp v cin v drv mode ultra s onic input 4.5 v dc to 60 v dc sic462
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 2 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pin configuration fig. 2 - sic462 pin configuration pin description pin number symbol description 1v cin supply voltage for internal regulators v dd and v drv . this pin should be tied to v in , but can also be connected to a lower supply voltage (> 5 v) to reduce losses in the internal linear regulators 2p good open-drain power good indicator - high impedance indicates power is good. an external pull-up resistor is required 3 en enable pin 4 boot high-side driver bootstrap voltage 5, 6 phase return path of high-side gate driver 7, 8, 29 v in power stage input voltage. drain of high-side mosfet 9, 10, 11, 17, 30 p gnd power ground 12, 13, 14 sw power stage switch node 15 gl low-side mosf et gate signal 16 v drv supply voltage for internal gate driver. when using the internal ldo as a bias power supply, v drv is the ldo output. connect a 4.7 f decoupling capacitor to p gnd 18 ultrasonic float to disable ultrasonic mode, connect to v dd to enable. depending on the operation mode set by the mode pin, power save mode or forced contin uous mode will be enab led when the ultrasonic mode is disabled 19 ss set the soft start ramp by connecting a capacitor to a gnd . an internal current source will charge the capacitor 20 v sns power inductor signal feedback pin for system stability compensation 21 comp output of the internal error amplifier. the feedback loop compensation network is connected from this pin to the v fb pin 22 v fb feedback input for switching regula tor used to program the output vo ltage - connect to an external resistor divider from v out to a gnd 23, 28 a gnd analog ground 24 f sw set the on-time by connecting a resistor to a gnd 25 i limit set the current limit by co nnecting a resistor to a gnd 26 v dd bias supply for the ic. v dd is an ldo output, connect a 1 f decoupling capacitor to a gnd 27 mode set various operation modes by connecting a resistor to a gnd . see specification table for details 6 ss 19 ultra s onic 1 8 p g nd 17 v drv 16 g l 1 5 s w 1 4 s w 1 3 s w 1 2 p g nd 11 p g nd 10 p g nd 9 v in 8 v in 7 1 v cin 2 p g ood 3 en 4 boot 5 pha s e 6 pha s e 20 v s n s 21 comp 22 v fb 23 a g nd 24 f s w 25 i lim 26 v dd 27 mode 28 a g nd 29 v in 30 p g nd 19 ss 18 ultra s onic 17 p g nd 16 v drv 15 g l 14 s w 13 s w 12 s w 1 2 3 4 5 6 27 26 25 24 23 22 v fb 21 comp 20 v s n s 28 a g nd 30 vin 29 p g nd p g nd 11 p g nd 10 p g nd 9 v in 8 v in 7 1 6 mode v dd i lim f s w a g nd v cin p g ood en boot pha s e pha s e
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 3 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 part marking information ? stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those in dicated in the operational sectio ns of the specifications is not implied. exposure to absolute maximum rating/conditions for extended peri ods may affect de vice reliability. note (1) for input voltages below 5 v, provide a separate supply to v cin of at least 5 v to prevent the internal v dd rail uvlo from triggering. ordering information part number package marking code SIC462ED-T1-GE3 powerpak ? mlp55-27l sic462 sic462evb reference board absolute maximum ratings (t a = 25 c, unless otherwise noted) electrical parameter conditions limits unit en, v cin , v in reference to p gnd -0.3 to +63 v sw / phase reference to p gnd -0.3 to +66 v drv reference to p gnd -0.3 to +6 v dd reference to a gnd -0.3 to +6 sw / phase (ac) 100 ns -4 to +72 boot -0.3 to v phase + v drv a gnd to p gnd -0.3 to +0.3 all other pins re ference to a gnd -0.3 to v dd + 0.3 temperature junction temperature t j -40 to +150 c storage temperature t stg -65 to +150 power dissipation thermal resistance from junction to ambient 12 c/w thermal resistance from junction to case 2 esd protection electrostatic disc harge protection human body model, jesd22-a114 2000 v charged device mo del, jesd22-a101 750 recommended operating conditions (all voltages referenced to gnd = 0 v) parameter min. typ. max. unit input voltage (v in )4.5-60 v control input voltage (v cin ) (1) 4.5 - 60 enable (en) 0 - 60 bias supply (v dd ) 4.75 5 5.25 drive supply voltage (v drv ) 4.75 5.3 5.5 output voltage (v out ) 0.8 - 0.8 x v in temperature recommended ambient temperature -40 to +105 c operating junction temperature -40 to +125 = pin 1 indicator p/n = part number code = s iliconix lo g o =e s d symbol f = assembly factory code y = year code ww = week code ll = lot code f y w w p/n ll
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 4 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical specifications (v in = v cin = 48 v, t j = -40 c to +125 c, unless otherwise stated) parameter symbol test conditions min. typ. max. unit power supplies v dd supply v dd v in = v cin = 6 v to 60 v, v en = 5 v, not switching -5- v v in = v cin = 5 v, v en = 5 v, not switching -4.96- v dd dropout v dd_dropout v in = v cin = 5 v, i vdd = 1 ma - 60 - mv v dd uvlo threshold v dd_uvlo -4.25- v v dd uvlo hysteresis v dd_uvlo_hyst - 250 - mv maximum v dd current i dd v in = v cin = 6 v to 60 v 3 - - ma v drv supply v drv v in = v cin = 6 v to 60 v, v en = 5 v, not switching -5.3- v v in = v cin = 5 v, v en = 5 v, not switching -5- v drv dropout v drv_dropout v in = v cin = 5 v, i vdd = 10 ma - 160 - mv maximum v drv current i drv v in = v cin = 6 v to 60 v 50 - - ma v drv uvlo threshold v drv_uvlo -4.25- v v drv uvlo hysteresis v drv_uvlo_hyst - 275 - mv input current iv cin non-switching, v fb > 0.8 v - 245 - a shutdown current iv cin_shdn v en = 0 v - 5 10 controller an d timing feedback voltage v fb t j = 25 c 796 800 804 m/v t j = -40 c to +125 c (1) 792 800 808 v fb input bias current i fb -2-na transconductance g m -0.3-ms comp source current i comp_source -20- a comp sink current i comp_sink -20- minimum on-time t on_min. - 100 - ns t on accuracy t on_accuracy -10-% on-time range t on_range 100 - 8000 ns frequency range f khz ultrasonic mode enabled 20 - 2000 khz ultrasonic mode disabled - - 2000 minimum off-time t off_min. - 250 - ns soft start current i ss -5-a soft start voltage v ss when v out reaches regulation - 1.5 - v power mosfets high-side on resistance r on_hs v gs = 5.3 v -25- m ? low-side on resistance r on_ls -11- fault protections current limit accuracy i lim_accuracy 1 % resistor used for r lim -20 - 20 % output ovp threshold ovp v fb with respect to 0.8 v reference -20- output uvp threshold uvp - -80 - over temperature protection otp r rising temperature - 150 - c otp hyst hysteresis - 35 -
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 5 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note (1) guaranteed by design power goo d power good output threshold v fb_rising_vth_ov v fb rising above 0. 8 v reference - 20 - % v fb_falling_vth_uv v fb falling below 0. 8 v reference - -10 - power good hysteresis p good_hyst -55-mv power good on resistance r on_pgood -8- ? power good delay time t dly_pgood -25-s en / mode / ultrasonic threshol d en logic high level v en_h 1.4 - - v en logic low level v en_l --0.4 en pull down resistance r en -5-m ? ultrasonic mode high level u high 2-- v ultrasonic mode low level u low --0.8 mode pull up current i mode -5-a mode1 power save mode enabled, v dd , v drv pre-reg on 0-0.7 v mode2 power save mode disabled, v dd , v drv pre-reg on 1.3 - 1.7 mode3 power save mode disabled, v drv pre-reg off, v dd pre-reg on, provide external v drv 2.3 - 2.7 mode4 power save mode enabled, v drv pre-reg off, v dd pre-reg on, provide external v drv 3.3 - v dd electrical specifications (v in = v cin = 48 v, t j = -40 c to +125 c, unless otherwise stated) parameter symbol test conditions min. typ. max. unit
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 6 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 functional block diagram fig. 3 - sic462 functi onal block diagram v in v fb p g ood 5 a current s ource 0.8 v i limit mode en bandgap ref driver ldo 25 khz dc re s tore control logic and driver v drv v cin on timer f s w v cin error amp over temp internal ldo current s en s e comp v s n s s w ss comp zero current det s ync. rectifier off timer v drv v dd g l uvlo v dd 5 a ref mode boot over voltage pwm comp ref ramp ultra s onic pha s e p g nd under voltage a g nd 5 a ref v fb s w s w
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 7 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 operational description device overview sic462 is a high-efficiency synchronous buck regulator capable of delivering up to 6 a continuous current. the device has programmable swit ching frequency of 100 khz to 2 mhz. the control scheme is based on voltage mode constant on time. it delivers fast transient response and minimizes external component s. it also enables loop stability regardless of the type of output capacitor used, including low-esr ceramic capa citors. this device also incorporates a power saving feature by enabling diode emulation mode and frequency fold back as the load decreases. sic462 has a full set of protection and monitoring features: ? over current protection in pulse-by-pulse mode ? output overvoltage protection ? output undervoltage protect ion with device latch ? over temperature protection with hysteresis ? dedicated enable pin for easy power sequencing ? power good open drain output ? this device is available in mlp55-27l package to deliver high power density and minimize pcb area. power stage sic462 integrates a high-performance power stage with a 25 m ? n-channel high side mosfet and a 11 m ? n-channel low side mosfet. the mosfets are optimized to achieve up to 98 % efficiency. ? the power input voltage (v in ) can go up to 60 v and down as low as 4.5 v for power conversion. control scheme sic462 employs a voltage - mode cot control mechanism in conjunction with adaptive zero current detection which allows precise power saving feature. the switching frequency, f sw , is set by an external resistor to a gnd , r fsw . ? note, that there is no v in dependency on f sw as the on time adjusts as v in is varied. during st eady-state operation, v comp is generated from the fee dback voltage and internal 0.8 v reference inputs to the er ror amplifier. an internally generated ramp signal and v comp are fed into a comparator. once v ramp crosses v comp , a single shot on-time pulse is generated for a fixed time, programmed by the external r fsw . during the on-time pulse, the high side mosfet will be turned on. once the on-time pulse expires, the high side mosfet is turned off an d the low side mosfet will be turned on after a break-befo re-make period. the low side mosfet will be on for durati on of minimum off-time pulse until v ramp crosses v comp . the cycle is then repeated. fig. 4 illustrates the basic bl ock diagram for voltage mode constant on time architecture with external ripple injection. ? the reference of a basic vo ltage mode cot regulator is replaced with a high gain e rror amplifier loop. this loop ensures the dc component of the output voltage follows the internal accurate reference voltage provides excellent regulation ? a second voltage feedback path via the v sns with a ripple injection scheme ensures rapid correction of the transient perturbation ? this establishes two parallel voltage regulating feedback paths, a ripple injection path , and a steady accurate dc reference path fig. 4 - sic462 co ntrol block diagram ? for stability purposes the sic462 requires 200 mv of ripple injection. c x , c y , and r x are selected to achieve the desired ripple injection. typically c y is chosen to be ? 2 nf to meet the internal impedance of the v sns pin. c x is chosen to be 10 times greater than c y , c x = 10 x c y . ? fig. 5 demonstrates the basic operational waveforms: fig. 5 - sic462 operational principle ? typically, the frequency of r comp and c comp is chosen to be around the resonance frequency of l out and c out . in this case, set for good slew rate / transi ent load response, pick c comp ? 1 nf, r comp can be calculated according the formula above. r fsw v out f sw 190 10 12 ? ? ? -------------------------------------------- - = 48 v1 q1 q2 ripple ba s ed controller c y r comp 1 nf x1 c comp + ref. erroramp r x c x l out r1 r2 c out load r x v in - v out ?? x v out /v in f sw ? x c x x v ripple ?? ?? = fixed on-time v ramp v comp pwm r comp x c comp l out x c out =
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 8 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 power-save mo d e, mode pin, an d ultrasonic pin operation to improve efficiency at light-loads, sic462 provides a set of innovative implementations to eliminate ls re-circulating current and switching losses. the internal zero crossing detector (zcd) monitors sw node voltage to determine when inductor current starts to flow negatively. in power saving mode, as soon as in ductor valley current crosses zero, the device first deploys diode emulation mode by turning off the ls fet. if load further decreases, switching frequency is reduced proportional to the load condition to save switching losses while keeping output ripple within tolerance. if the ultrasonic pin is tied to v dd , the minimum switching frequency in the discontinuous mode is 25 khz to avoid switching frequencies in the audible range. if this feature is not required this ul trasonic mode can be disabled by floating the ultrasonic pin. when the ultrasonic mode is disabled, the regulator will either operate in forced continuous mode or in a power save mode where there is no limit to the lower frequency limit. in this state, at zero load switching frequency can go as low as hundreds of hz. to improve the converter efficiency, the user can choose to disable the internal v drv regulator by picking either mode 3 or mode 4 and connecting a 5 v supply to the v drv pin. this reduces power dissipation in th e sic462 by eliminating the v drv linear regulator losses. the mode pin supports several modes of operation as shown in table 1. an internal current source is used to set the voltage on this pin using an external resistor: note (1) connect a 5 v ( 5 %) supply to the v drv pin the mode pin is not latche d to any state and can be changed on the fly. output monitoring and protection features output over-current protection (ocp) sic462 has cycle by cycle current limiting. the inductor valley current is monitored du ring ls fet turn-on period through r ds(on) sensing. after a pre-d efined blanking time, the valley current is compared wi th an internal threshold. if monitored current is higher than threshold, hs turn-on pulse is skipped and ls fet is kept on until the valley current returns below ocp limit. in a short circuit or a severe over-current condition, output undervoltage protection (uvp) will result in both the hs and ls fet turning off. see output undervoltage protection (uvp) section for more details. ocp is enabled immediately after v cc passes uvlo level. ocp is set by an external resistor to a gnd , r lim . fig. 6 - over-current protection illustration output un d ervoltage protection (uvp) uvp is implemented by moni toring output through v fb pin. if the voltage level at v fb goes below 0.16 v (v out is 20 % of v out set point) for more than 25 s a uvp event is recognized and both hs and ls mosfets are turned off. after a time-out period equal to 20 soft start cycles, the ic attempts to re-start by going thro ugh a soft start cycle. if the fault condition still exists, the above cycle will be repeated. uvp is only active after th e completion of soft-start sequence. output over-voltage protection (ovp) for ovp implementation, output is monitored through fb pin. after soft start, if the voltage level at fb is above 0.96 v (typ.) (v out is 120 % of v out set point), ovp is triggered with both the hs and ls mosfets turned off. normal operation is resumed once fb voltage drops back to 0.96 v. ovp is active immediately after v cc passes uvlo level. over-temperature protection (otp) sic462 has internal thermal monitor block that turns off both hs and ls fets when junction temperature is above 150 c (typ). a hysteresis of 35 c is implemented, so when junction temperature drops below 115 c, the device restarts by initiating soft-start sequence again. sequencing of input / output supplies sic462 has no sequencing requirements on any of its input / output (v in , v drv , v dd , v cin , en) supplies or enables. ena b le the sic462 has an enable pin to turn the part on and off. driving this pin high enables the device, while grounding it turns it off. the sic462 enable has a weak pull down to prevent unwanted turn on due to a floating gpio. there are no sequencing requirements w.r.t other input / output supplies. ? table 1 - operation modes mode range (v) power save mode internal v drv regulator 1 0 to 0.7 enabled on 2 1.3 to 1.7 disabled on 3 2.3 to 2.7 disabled off (1) 4 3.3 to v dd enabled off (1) r lim 480k / i out max. = i load ocp thre s hold i inductor g h
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 9 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 soft-start sic462 soft-start time is adjustable by selecting a capacitor value from the following equation. once v cc is above uvlo level (2.55 v typ.), v out will ramp up slowly, rising monotonically to the programmed output voltage. there is an internal 5 a current source tied to the soft start pin which charges the external soft start cap. during soft-start period, ocp is activated. short-circuit protection is not active until soft-start is complete. pre-bias start-up in case of pre-bias startup, ou tput is monitored through fb pin. if the sensed voltage on fb is higher than the internal reference ramp value, control logic prevents hs and ls fet from switching to avoid negative output voltage spike and excessive current sinking through ls fet. fig. 7 - pre-bias start-up fig. 8 - p good win d ow an d timing diagram power goo d sic462s power good is an open-drain output. pull p good pin high up to 5 v through a 10k resistor to use this signal. power good window is shown in the diagram above. if voltage level on fb pin is out of this window, pg signal is de-asserted by pulling down to gnd. to prevent false triggering during transient events, p good has a 25 s blanking time. ss time c ext x 0.8 v 5 a -------------------------------- = v ref (0.8 v) v fb v fb_ri s ing_vth_ov (typ. = 0.96 v) vfb_falling_vth_ov (typ. = 0.91 v) vfb_falling_vth_uv (typ. = 0.72 v) vfb_ri s ing_vth_u v (typ. = 0.77 v) p g pull-high pull-low
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 10 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 reference board schematic c10 dnp r10 40k c11 1n tp1 vin 1 tp2 gnd 1 tp5 vout 1 tp6 gnd 1 tp4 1 tp3 1 pgd j11 gnd 1 vo_gnd en c14 2.2n c13 4.7u gl r6 0 c1 100n j10 en 1 r5 100k c25 poscap pgd j7 pgd 1 r15 100 j1 jumper 1 2 j2 jumper 1 2 j3 jumper 1 2 j4 jumper 1 2 r3 500k r4 750k r1 10k r2 300k c12 4.7nf mode r8 82k ilim r9 126k vdd1 j5 con4 1 2 3 4 c3 1u c2 0.1uf comp j8 vdrv 1 c7 2.2uf c8 2.2uf c5 56u r12 open vdrv c4 56u vo j9 jumper 1 2 ultra vdd1 vo_gnd c6 2.2uf c21 22uf c22 22uf c23 22uf vo c24 22uf vin c9 0.1uf r7 dnp vin r14 4k r16 dnp c16 dnp c15 22nf l1 15uh en r13 9.50k c18 22uf c17 0.1u c19 22uf c20 22uf r11 679 ic1 sic462 vcin 1 pgood 2 en 3 boot 4 phase1 5 phase2 6 vin1 7 vin2 8 pgnd1 9 pgnd2 10 pgnd3 11 sw1 12 sw2 13 sw3 14 vdrv 16 ss 19 ultrasonic 18 mode 27 vsns 20 comp 21 pgnd 17 vfb 22 agnd 23 fsw 24 ilim 25 vdd 26 gnd-pad 28 gl 15
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 11 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note (1) these two large aluminium electrolytic caps are included in case the customers evaluation set up has long leads. they are not n eeded for sic462 operation. bill of material qty reference designator description part number manufacturer 1 c1 capacitor ceramic 0.1 f 100 v x5r 0402 grm155r62a104me14d murata electronics 1 c3 capacitor ceramic 1 f 35 v x5r 0402 c1005x5r1v105m050bc tdk corporation 1c10 dnp - - 1 c11 capacitor ceramic 1000 pf 100 v x7r 04 02 grm155r72a102ka01d murata electronics 1 c12 capacitor ceramic 10000 pf 100 v x7s 0402 c1005x7s2a103k050bb tdk corporation 2 c2, c9 capacitor ceramic 0.1 f 100 v x7 r 0603 grm188r72a104ka35d murata electronics 1 c15 capacitor ceramic 0.022 f 100 v x7r 0603 c0603c223k1ractu kemet 1 c14 capacitor ceramic 2200 pf 100 v x7r 0603 c0603c222k1ractu kemet 1c16 dnp - - 1 c17 capacitor ceramic 0.1 f 35 v x5r 0603 gmk107bj104kaht taiyo yuden 1 c13 capacitor ceramic 4.7 f 35 v x5r 080 5 grm219r6ya475ka73d murata electronics 3 c6, c7, c8 capacitor ceramic 2.2 f 100 v x7r 1210 hmk325b7225kn-t taiyo yuden 7 c18, c19, c20, c21, c22, c23, c24 capacitor ceramic 22 f 25 v x5r 1210 gr m32er61e226ke15l murata electronics 1 j5 terminal block 5.08 mm vert 4pos ed120/4ds on shore technology inc. 2c4, c5 (1) capacitor aluminum 56 f 20 % 100 v radial uhe2a560mpd nichicon 1 l1 inductor 10 h ihlp4040dzer100m11 vishay 5 j1, j2, j3, j4, j9 b/s ii hdr. sr 68000-402 amphenol fci 1c25 dnp - - 1 r1 resistor 10k 1 % 1/16 w 0402 rc0402fr-0710kl yageo 1 r2 resistor 300k 1 % 1/16 w 0402 rc0402fr-07300kl yageo 1 r3 resistor 499k 1 % 1/16 w 0402 rc0402fr-07499kl yageo 1 r4 resistor 750k 1 % 1/16 w 0402 rc0402fr-07750kl yageo 2 r5, r7 resistor 100k 1 % 1/16 w 0402 rc0402fr-07100kl yageo 1 r6 resistor 0.0 jumper 1/16 w 0402 rc0402jr-070rl yageo 1 r8 resistor 48.7k 1 % 1/16 w 0402 rc0402fr-0748k7l yageo 1 r9 resistor 210k 1 % 1/16 w 0402 rc0402fr-07210kl yageo 1 r10 resistor 56k 5 % 1/16 w 0402 rc0402jr-0756kl yageo 1 r11 resistor 10k 5 % 1/10 w 0603 rc0603fr-0710kl yageo 1r12 - - - 1 r14 resistor 6.8k 5 % 1/10 w 0603 rc0603jr-076k8l yageo 1 r13 resistor 140k 1 % 1/10 w 0603 rc0603fr-07140kl yageo 1 r15 resistor 100 1 % 1/10 w 0603 rc0603fr-07100rl yageo 1r16 dnp - - 1 ic1 ic sic462 sic462 vishay 10 j7, j8, j10, j11, tp, tp2, tp3, tp4, tp5, tp6 bergstik ii 0.100" sngl st 68002-401hlf amphenol fci
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 12 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 external component selection for the sic462 a reference design has been de veloped to illustrate how to choose component va lues for proper operation of the sic462. the schematic for the demo board is shown in fig. 9 and table 2. demo boar d connection an d signal / test points power sockets v in , gnd (p1): input voltage source with v in to be positive. connect to a voltage source: v out , gnd (p3): output voltage with v out to be positive. connect to a load that draws no more than: 5 v, gnd (p10): external 5 v mosfet gate voltage source with 5 v to be the positive input. apply 5 v when mode 3 or mode 4 is selected. selection jumpers mo d e select p7: this is an 8 way header which allows the user to select one of four modes of operation. mode1 - short pin 1 to 2 power save, v drv and pre-reg on mode2 - short pin 3 to 4 forced pwm, v drv and pre-reg on mode3 - short pin 5 to 6 forced pwm, v drv and pre-reg off - external 5 v supply mode4 - short pin 7 to 8 power save, v drv and pre-reg off - external 5 v supply v drv external supply p10: this is a 2 way header that will enable the user to supply an external mosfet gate driv er supply if an external 5 v supply is available. this should only be used in modes 3 and 4. enable p9: this is a 2 way header that wi ll enable the part if left open. when shorted the pa rt is disabled. open pin 1-2 - automatic enable on power up ? short pin 1-2 - ic disabled. ultrasonic p8: this is a 2 way header that will enable the user to select the ultrasonic mode of operation. in ultrasonic mode the minimum frequency of operation is 20 khz, above the audible range. when not in ul trasonic mode the frequency can drop below 20 khz. open pin 1-2 - ultrasonic disabled ? short pin 1-2 - ultrasonic enabled signals and test leads input voltage sense v in _ sense , gnd in _ sense (p2): this allows the user to measure the voltage at the input of the regulator and remove any losses generated due to the, connections from the measurement. this can also be used by a power source with sense capability. ? ? output voltage sense v out_sense , gnd out_sense (p4): this allows the user to measure the voltage at the output of the regulator and remove any losses generated due to the connections, from the measurement. this can also be used by an active load with sense capability. power good indicator p good (p11): is an open drain output and is pulled up with a 10 k ? resistor to v in . when fb or v out are within -10 % to +20 % of the set voltage this pin will go hi to indicate the output is okay. power up procedure to turn-on the reference board, apply 12 v to v in with the p7 jumper is in position 1. if the p7 jumper is in place 1 the board will come up in power sa ve mode, if in place 2 then constant pwm will be observed. ? when applying higher than 12 v to the input it is reasonable to install a rc snubber from sw to gnd if needed however this will affect efficiency. th ere are place holders on the reference board, r 11 and c 12 for the snubber. values of 4 ? and 1 nf are a reasonable starting point. adjustments to the reference board output voltage adjustment if a different output voltage is needed, simply change the value of v out and solve for r 12 based on the following formula: where v fb is 0.8 v for the sic46x. r bottom (r 13 ) should be a maximum of 10 k ? to prevent v out from drifting at no load. changing switching frequency the following equation illustrates the relationship between on-time, v in , v out , and r fsw value: output ripple voltage there is no requirement for th is converter to see output capacitor ripple voltage in the control loop as a voltage injection circuit is employed; the voltage injection ramp is used to alert the converter to the next switch event. output ripple voltage is meas ured with a tip and barrel measurement across c out ; the barrel of the probe is the gnd / 0 v connection and this removes the effect of the long gnd / 0 v leads of the probe. typically output ripple voltage r 12 r 13 v out - v fb ?? v fb -------------------------------------------- - = r fsw r 7 v out f sw 190 10 12 ? ? ? -------------------------------------------- - ==
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 13 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 is set to 3 % to 5 % of the output voltage, but an all ceramic output solution can bring output ripple voltage to a much lower level since the esr of cera mics can be in the range of m ? s. voltage injection network this is the network seen placed across the output inductor in the schematic consisting of r 10 , c 10 and c 11 . a quick method to add or remove inject ion is to reduce or increase r 10 . the time constant of the voltage injection network is as follows: in order to set a correct magn itude, the sic46x requires around 200 mv, the following equation is used: where v injection = 200 mv is the midpoint of the ripple injection rc circuit. fig. 9 - voltage injection circuit ? in fig. 9 the recommended value of c x = c 10 (a or b) ? 22 nf and c y = c 11 ? 2.2 nf. the reference design allows placement of c x in two positions as shown in fig. 9, a and b. the b option removes the output ripple and transient response voltage from the injection signal. th e effect of connecting the c x capacitor to gnd / 0 v is the same as removing the output information from the fast loop. the output will be very stable in this setup when large transient loads are experienced at the output; in any case you will notice that the effective impedance of the outp ut node is very small and the fb loop will react quickly enough for all loads. another key aspect of using the gnd / 0 v connection for the injection circuit is the ability to use a smaller output capacitance. be aware that the b) option is should only be used with forced pwm operation. where t is the on period. the required magnitude is ~ 100 mvpp for stable operation. compensation the cot loop uses a transconductance amplifier to convert a proportional current from the output voltage, v fb . this has the effect of offering a high impedance at the v fb node, however this circuitry is left with a wide bandwidth to accommodate the different switching frequencies. this will require rolling off with an rc circuit, use the following equation: c comp will be set to 1 nf. this provides a frequency breakpoint around the lc filter peak. it may be necessary to reduce the roll off further, this can be a choice of the designer but an example might be to start at 1/2 the lc filter peak frequency. this will affect the transient response time, something to note is the minimal phase delay in the cot topology and its fast re sponse compared to pwm converters. inductor selection the choice of inductor is specific to each application and quickly determined with the following equations: and where k is a percentage of maximum output current ripple required. the designer can quickly make a choice of inductor if the ripple percentage is decided, usually no more than 30 % however higher or lower percentages of i out can be acceptable depending on app lication. this device allows choices larger than 30 %. other than the inductance th e dcr and satura tion current parameters are key values. the dcr causes an i 2 r loss which will decrease the system efficiency and generate heat. the saturation current has to be higher than the maximum output current plus ? of the ripple current. in an over current condition the induct or current may be very high. all this needs to be considered when selecting the inductor. on this board vishay ihlp series inductors are used to meet cost requirement and high efficiency, a part that utilizes a material that has incredible saturation behaviour compared to competing products. ? ? ? ? ? ? ? ? ? ? ? injection r x x c x = r x v in - v out ?? x v out v in x f sw x c x x v injection ---------------------------------------------------------------------------- ?? ?? = v out v inj l r x c x c y a b v injection v in_min. - v out ?? x 1 - 1 e t ? inj --------- ---------- - ?? ?? ?? ?? ?? = r comp l x c out c comp ----------------------------- = t on v out v in_max. x f sw ------------------------------------ - = l v in - v out ?? x t on i out_max. x k -------------------------------------------------- =
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 14 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 output capacitor selection voltage rating, esr, transient response, overall pcb area and cost are requirements for selecting output capacitors. the types of capacitors and there general advantages and disadvantages are covered next. electrolytic have high esr, dry out over time so ripple current rating must be examin ed and have slower transient response, but are fairly inexpensive for the amount of overall capacitance. ? tantalums can come in low esr varieties and high capacitance value for its overall size, but they fail short when damaged and also have sl ower transient response. ceramics have very low esr, fast transient response and overall small size, but come in low capacitance values compared to the others types. a combination of technology is sensible, however these co nverters suit an ceramic solution also. the output capacitance will be determined by the ripple voltage requirement. voltage mode cot topology can work with very small values of capacitor esr. the following equations are used to calculate the size needed to meet a transient load response: and where i lpk is the peak inductor current, i max. is the maximum output current, di load is the current step in s and v pk is the peak voltage, the output voltage summed with the specified over and under shoot. the evaluation pcb is fitter with 66 f. enable pin voltage the en pin has an internal pull down resistor and only requires an enable voltage. this needs to be greater than 1.4 v. an input voltage or a resistor connected across v in and en can be used. the intern al pull down resistance is 5 m ? . soft start setting soft start is a useful function helping to limit the current magnitude from the source at switch on. this is simply set with a ceramic capacitor us ing the following equation: a 100 nf capacitor will provide ~ 16 ms soft start time. v dd pin will need to be decoupled in order to provide a stable voltage internally and externally. the value for this capacitor is recommended as ? 1 f. ? ? ? current limit resistor the current limit is set by placing a resistor between i lim and a gnd . the values can be found using the following equation: input capacitance in order to keep the design compact and minimize parasitic elements, ceramic capacitors will be chosen. the initial requirement for the input capacitance is decided by the maximum input voltage, 60 v in this case however a 100 v rated capacitor will be chosen of the x7r variety. the footprint will be a compact 1206. in order to determine the mi nimum capacitance the input voltage ripple needs to be specified; v cinpp ? 500 mv is a suitable starting point. this magnitude is determined by the final application specification. the input current needs to be determined for the lowest operating input voltage, the minimum input capacita nce can then be found, for output voltage greater than 5 v the input capacitance should be increased accordi ngly. as the output power increases so does the input voltage ripple, the evaluation pcb has 4.4 f. note ? if the input voltage becomes very small then extra capacitance needs adding to the input as the ripple will affect the duty cycle calculation when larger current is required. ? i lpk i max. + 0.5 x i ripple_max. = c out_min. i lpk x l x i lpk 2 v out ------------- - - i max 2 x dt dl load -------------------------- - 2 x v pk - v out ?? ---------------------------------------------------------- = t ss c ss x 0.8 5 x 10 6 ? ------------------------- - = r lim 480 000 i out_max. ------------------------ - = i cin rms ?? = i o x d x 1 d ? ?? 1 12 ------ v out l? sw i out ? ? ------------------------------------- ?? ?? 2 ? 1d ? ?? 2 ? d ? + c in_min. i out x d - 1 - d ?? v cinpkpk x f sw ----------------------------------------- =
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 15 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics (v in = 48 v, v out = 5 v, f sw = 300 khz unless noted otherwise) fig. 10 - efficiency vs. output current (v out = 12 v, f sw = 500 khz) fig. 11 - efficiency vs. output current (v out = 5 v, f sw = 300 khz) fig. 12 - on resistance vs. junction temperature fig. 13 - efficiency vs. output current (v out = 12 v, f sw = 500 khz) fig. 14 - efficiency vs. output current (v out = 5 v, f sw = 300 khz) fig. 15 - input current vs. junction temperature 75 80 85 90 95 100 0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 efficiency (%) output current, i out (a) complete converter efficiency p in = [(v in x i in ) + (v cin x i cin )] p out = v out x i out , mea s ured at output capacitor v in = 36 v, l = 15 h v in = 48 v, l = 15 h v in = 24 v, l = 10 h 75 80 85 90 95 100 0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 efficiency (%) output current, i out (a) complete converter efficiency p in = [(v in x i in ) + 5 v x (i vdrv + i vcin )] p out = v out x i out , mea s ured at output capacitor complete converter efficiency p in = [(v in x i in ) + ( v cin x i cin )] p out = v out x i out , mea s ured at output capacitor v in = 48 v, l = 8.2 h v in = 24 v, l = 10 h v in = 12 v, l = 8.2 h v in = 36 v, l = 15 h 0 6 12 18 24 30 36 42 48 -60 -40 -20 0 20 40 60 80 100 120 140 on- s tate re s i s tance, r d s on (m ) temperature ( c) high s ide low s ide 75 80 85 90 95 100 0.01 0.1 1 efficiency (%) output current, i out (a) complete converter efficiency p in = [(v in x i in ) + (v cin x i cin )] p out = v out x i out , mea s ured at output capacitor v in = 36 v, l = 15 h v in = 48 v, l = 15 h v in = 24 v, l = 10 h 60 65 70 75 80 85 90 95 100 0.01 0.1 1 efficiency (%) output current, i out (a) complete converter efficiency p in = [(v in x i in ) + ( v cin x i cin )] p out = v out x i out , mea s ured at output capacitor v in = 48 v, l = 8.2 h v in = 24 v, l = 10 h v in = 12 v, l = 8.2 h v in = 36 v, l = 15 h 140 160 180 200 220 240 260 280 300 -60 -40 -20 0 20 40 60 80 100 120 140 input current, i vcin + i vin (a) temperature ( c)
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 16 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics (v in = 48 v, v out = 5 v, f sw = 300 khz unless noted otherwise) fig. 16 - shut d own current vs. input voltage fig. 17 - loa d regulation, v out = 12 v fig. 18 - en logic threshol d vs. junction temperature fig. 19 - shut d own current vs. junction temperature fig. 20 - line regulation, v out = 12 v fig. 21 - en current vs. junction temperature 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 6 12 18 24 30 36 42 48 54 60 s hutdown current, i vcin_ s hdn + i vin_ s hdn (a) input voltage, v cin / v in (v) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 load regulation (%) output current (a) 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 -60 -40 -20 0 20 40 60 80 100 120 140 en logic thre s hold, v en (v) temperature ( c) v ih_en v il_en 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 -60 -40 -20 0 20 40 60 80 100 120 140 s hutdown current, i vcin_ s hdn + i vin_ s hdn (a) temperature ( c) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 20 25 30 35 40 45 50 55 60 line regulation (%) input voltage (v) 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 -60 -40 -20 0 20 40 60 80 100 120 140 en current, i en (a) temperature ( c) v en = 5 v
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 17 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics (v in = 48 v, v out = 5 v, f sw = 300 khz unless noted otherwise) fig. 22 - voltage reference vs. junction temperature fig. 23 - start-up with en, time = 1 ms/ d iv fig. 24 - start-up with v in , time = 5 ms/ d iv fig. 25 - loa d transient (3 a to 6 a), (6 a to 3 a), time = 100 s/ d iv fig. 26 - line transient (8 v to 48 v), time = 10 ms/ d iv fig. 27 - output ripple 2 a, time = 5 s/ d iv 792 794 796 798 800 802 804 806 808 -60 -40 -20 0 20 40 60 80 100 120 140 voltage reference, v fb (mv) temperature ( c)
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 18 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics (v in = 48 v, v out = 5 v, f sw = 300 khz unless noted otherwise) fig. 28 - output ripple 300 ma, time = 5 s/ d iv fig. 29 - output ripple psm, time = 10 ms/ d iv
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 19 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pcb layout recommendations step 1: v in /gnd planes an d decoupling fig. 30 1. layout v in and p gnd planes as shown above. 2. ceramic capacitors shou ld be placed between v in and p gnd , and very close to the de vice for best decoupling effect. 3. different values / packages of ceramic capacitors should be used to cover entire decoupling spectrum e.g. 1210 and 0603. 4. smaller capacitance values, placed closer to devices v in pin(s), is better for high frequency noise absorbing. step 2: v cin pin fig. 31 1. v cin (pin 1) is the input pin for both internal ldo and t on block. t on time varies based on input voltage. its necessary to put a decouplin g capacitor close to this pin. 2. the connection can be made through a via and the cap can be placed at bottom layer. ? step 3: v swh plane fig. 32 1. connect output inductor to sic462 with large plane to lower the resistance. 2. if any snubber network is required, place the components on the bottom side as shown above. step 4: v dd /v drv input filter fig. 33 1. c vdd cap should be placed be tween pin 26 and pin 23 (the a gnd of driver ic) to achiev e best noise filtering. 2. c vdrv cap should be placed close to v drv (pin 16) and p gnd (pin 17) to reduce effe cts of trace impedance and provide maximum instantane ous driver current for low side mosfet during switching cycle. ? vin vswh vin plane pgnd plane vcin decouple cap agnd plane pgnd plane vswh snubber agnd p g n d c vdd c vdrv
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 20 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 step 5: boot resistor an d capacitor placement fig. 34 1. these components need to be placed very close to sic462, right between phase (pin 5, 6) and boot (pin 4). 2. in order to reduce para sitic inductance, it is recommended to use 0402 chip size for the resistor and the capacitor. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? step 6: signal routing fig. 35 1. separate the small analog sign al from high current path. as shown above, the high cu rrent paths with high dv/dt, di/dt are placed on the left side of the ic, while the small control signals are placed on the right side of the ic. all the components for small analog signal should be placed closer to ic with minimum trace length. 2. pin 23 is the ic analog ground, which should have a single connection to power ground. the a gnd ground plane connected with pin 23 helps keep a gnd quiet and improve noise immunity. 3. feedback signal can be rout ed through inner layer. make sure this signal is far away from v swh node and shielded by inner ground layer. 4. ripple injection circuit can be placed next to inductor. kelvin connection as shown above is recommended. ? ? ? ? ? ? ? ? ? ? ? ? ? cboot rboot pgnd agnd plane f b s i g n a l ripple injection circuit
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 21 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 step 7: a dd ing thermal relief vias an d duplicate power path plane fig. 36 1. thermal relief vias ca n be added on the v in and p gnd pads to utilize inner layers for high-current and thermal dissipation. 2. to achieve better thermal perf ormance, additional vias can be put on v in and p gnd plane. also, it is necessary to duplicate the v in and ground planes at bottom layer to maximize the power dissipati on capability from pcb. 3. v swh pad is a noise source and not recommended to put vias on this pad. 4. 8 mil drill for pads and 10 mils drill for plane are optional via sizes. the vias on pads may drain solder during assembly and cause assembly issues. please consult with the assembly house for guidelines. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? step 8: groun d layer fig. 37 1. it is recommended to make th e entire inner layer (next to top layer) ground plane. 2. this ground plane provide s shielding between noise source on top layer and sign al trace within inner layer. 3. the ground plane can be broken into two sections as p gnd and a gnd . vin plane pgnd plane vswh pgnd plane agnd plane
sic462 www.vishay.com vishay siliconix s17-0360-rev. d, 13-mar-17 22 document number: 65124 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 package outline drawing powerpak ? mlp55-27 notes 1. use millimeters as primary measurement 2. dimensioning and tolerances conform to asme y14.5m - 1994 3. n is the number of terminals, nd is the number of terminals in x-direction, and ne is the number of terminals in y-direction 4. dimension b applies to plated terminal and is m easured between 0.20 mm and 0.25 mm from terminal tip 5. the pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of packag e body 6. exact shape and size of this feature is optional 7. package warpage max. 0.08 mm 8. applied only for terminals ? vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package / ta pe drawings, part marking, and reliability data, see www.vishay.com/ppg?65124 . dim. millimeters inches min. nom. max. min. nom. max. a (8) 0.70 0.75 0.80 0.027 0.029 0.031 a1 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b (4) 0.20 0.25 0.30 0.078 0.098 0.011 d 5.00 bsc 0.196 bsc e 0.50 bsc 0.019 bsc e1 0.65 bsc 0.0256 bsc e 5.00 bsc 0.196 bsc l 0.35 0.40 0.45 0.014 0.016 0.018 n (3) 28 28 d2-1 3.25 3.30 3.35 0.128 0.130 0.132 d2-2 0.95 1.00 1.05 0.037 0.039 0.041 d2-3 1.95 2.00 2.05 0.077 0.079 0.081 d2-4 1.37 1.42 1.47 0.054 0.056 0.058 e2-1 0.95 1.00 1.05 0.037 0.039 0.041 e2-2 2.55 2.60 2.65 0.100 0.102 0.104 e2-3 2.55 2.60 2.65 0.100 0.102 0.104 e2-4 1.58 1.63 1.68 0.062 0.064 0.066 f1 0.20 - 0.25 0.008 - 0.010 f2 0.20 min. 0.008 min. k 0.40 bsc 0.016 bsc k1 0.70 bsc 0.028 bsc k2 0.70 bsc 0.028 bsc k3 0.30 bsc 0.012 bsc top view s ide view bottom view b a d e 2 x a a2 a1 1 19 6 12 c 7 20 27 11 11 x 7 6 1 19 c f1 f2 7 1.225 1.000 d2-1 d2-3 d2-4 d2-2 e2-2 k3 k2 e2- 3 e2-4 x 3 x 4 e e1 e2-1 12 20 27 0.08 0.10 c a e e e1 k x 2 b 0.10 cab k1 e mlp55-27l (5 mm x 5 mm) e1 e x 2 4
legal disclaimer notice www.vishay.com vishay revision: 13-jun-16 1 document number: 91000 disclaimer ? all product, product specifications and data ar e subject to change with out notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of th e products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product , (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all implied warranties, includ ing warranties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain types of applicatio ns are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular applic ation. it is the customers responsibility to validate tha t a particular product with the prope rties described in the product sp ecification is suitable for use in a particular application. parameters provided in datasheets and / or specifications may vary in different ap plications and perfor mance may vary over time. all operating parameters, including ty pical parameters, must be va lidated for each customer application by the customer s technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product could result in personal injury or death. customers using or selling vishay product s not expressly indicated for use in such applications do so at their own risk. please contact authorized vishay personnel to obtain writ ten terms and conditions rega rding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

▲Up To Search▲

Price & Availability of SIC462ED-T1-GE3

	To Download SIC462ED-T1-GE3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .